This invention relates generally to semiconductor devices, and more particularly the invention relates to an integrated transistor logic device utilizing a compound transistor formed from a CMOS transistor pair operating in conjunction with bipolar transistors formed within the drain regions to increase transconductance and switching speed.
The CMOS transistor pair is widely used in integrated circuit logic applications. However, a limitation of such devices is speed of operation. U.S. Pat. No. 4,920,399 for Conductance Modulated Integrated Transistor Structure and U.S. Pat. No. 5,021,858 for Compound Modulated Integrated Transistor Structure disclose and claim modifications of the CMOS transistor pair structure to include a region of opposite conductivity within the drain region or a Schottky contact to the drain region which acts as a minority carrier injector. In effect, the drain region forms a base region, the injector region forms the emitter, and the buried layer of the integrated structure forms the collector of a bipolar transistor. The resulting merged emitter BICMOS structure has a much higher transconductance with no increase in input capacitance resulting in an increase in operating speed.
However, there exists a limitation in the design and production tolerances of the integrated transistor structures. The NPN bipolar transistor, which is merged to the drain of the P channel MOS transistor, suffers from an electrical switch back effect which limits the operating voltage and current of the NPN transistor and the resulting circuit application. The problem is caused primarily by the top surface contact for feeding the positive power supply through the collector resistance of the NPN bipolar transistor which is made up of the buried layer resistance in the integrated structure (caused by the resistivity and length of the buried layer), the series resistance of the epitaxial collector, and the epitaxial contact resistance between the plus voltage contact and the buried layer. This resistance can be comparatively large and variable which severely limits the applications of the transistor structure.
The present invention is directed to minimizing the bipolar switch back effect by reducing the collector resistance.